1. Technical Field
The present invention relates to semiconductor memory devices and, in particular, to semiconductor memory devices and a method for testing the same. The method can optimize operation conditions by detecting a test cell that may easily fail in a test among memory cells passing a burn-in test, and detecting the worst operation conditions by performing the test on the test cell, thereby reducing power consumption in a refresh or active operation.
2. Description of the Background Art
In general, semiconductor device tests may be classified as either product tests or as a proof tests. The product test detects a defect generated in a fabrication process such as a wafer process and an assembly process. Through the product test, it is possible to screen out the defective products to select the good products. For this reason, the product test is performed in a shipping (fabrication) process in great quantity, and requires a high throughput.
The proof test confirms whether functionality and performance of a dynamic random access memory (DRAM) satisfies requisite specifications. In research and development, the proof test is precisely executed to improve the quality of the products and to reduce a development period. During the proof test, when a fabrication defect is detected, or when the function of the products do not satisfy relevant specifications, an analysis, or failure analysis, is executed to examine failure causes. It is especially important to locate a position in the DRAM in which a defect is generated.
The DRAM test measures characteristics such as direct current (DC) and alternating current (AC) parameters and functionality, using a memory tester.
To detect an initial DRAM defects at an early stage, a burn-in test, which is performed as a function test, applies a higher voltage and temperature than the DRAM will experience.
The defect cells detected in the product and proof tests are repaired using redundancy cells to perform a normal operation.
The DRAM is operated using the passed cells under the operation conditions considered requisite for normal DRAM operation, which are selected on the basis of experimental data.
As described above, the DRAM should be designed to have a sufficient operation margin, so that it can be operated in the worst conditions. If the sufficient operation margin is not obtained, a number of defect cells can be detected, and thus a usable chip may be detected as a defect chip, which results in low production yield.
For example, to solve the foregoing problem, a method of shortening a refresh period has been suggested to obtain a sufficient margin. However, according to this method, power consumption is increased.
Moreover, when the margin is sufficiently set up in the operation conditions, operation speed of the DRAM decreases. In order to prevent reduction of the operation speed of the DRAM, a high voltage can be applied. However, the use of high voltage also causes high power consumption. For example, the operation speed of a DRAM is increased merely by setting up a sense amplifier driving voltage as a high voltage, which results in increased power consumption.
The disclosed semiconductor memory device may include a memory cell array, a test unit and a driving unit. The memory cell array may comprise a test cell determined to be a worst cell one among memory cells passing a first test. The test unit performs a second test on the test cell under predetermined operation conditions, repeatedly performing the second test after adjusting the operation conditions of the test cell according to the result of the second test and finally outputting the final operation conditions. The driving unit drives the memory cell array using the final operation conditions obtained from the test unit.
In addition, a method for testing a semiconductor memory device is disclosed. The method may include detecting a test cell that may easily fail among the cells passing a first test, repairing the test cell, and memorizing an address of the test cell. The method may also include a test step for performing a second test on the test cell in predetermined operation conditions by using the address of the test cell and returning to the test step after adjusting the operation conditions, when the test cell passes the second test. The method may also include providing the operating conditions used in the test step as driving conditions of a memory cell array, when the test cell fails in the second test.